1. Field of the Invention
This invention relates generally to a method of manufacturing high density, high performance semiconductor devices that have dual damascene interconnects. More specifically, this invention relates to a method of manufacturing high density, high performance semiconductor devices that have dual damascene structures that are formed with a reduced number of masks.
2. Discussion of the Related Art
The increased demand for higher performance semiconductor devices has required more complex process technologies and materials to be utilized in the manufacture of semiconductor integrated devices. One way to increase the performance of a semiconductor integrated device such as a microprocessor is to reduce the gate width of the field effect transistors in the device in order to achieve a high internal clock speed for the microprocessor. The reduced gate widths have increased the performance significantly, however, the interconnect structure of the microprocessor has proved to be a roadblock to further increase in performance. This is because as increased performance is required, more transistors require more wiring in the interconnect structure. The increased density of the wiring can result in a decrease in performance relating to RC delays. To counteract the degradation in performance due to the RC delays, additional layers, commonly referred to as metal layers, in which interconnects are formed are manufactured in the semiconductor device in order to separate the wiring in both the vertical and horizontal directions. These requirements have necessitated the development of novel approaches in the methods of forming interconnections that not only integrate fine geometry definition but also can be efficiently implemented into the manufacturing process.
One method of forming a trench is a method known as the damascene process, which comprises forming a trench by masking and etching techniques and subsequent filling of the trench with the desired conductive material. The damascene process is a useful method for attaining the fine geometry metallization required for advance semiconductor devices. A dual damascene process is a two step sequential mask/etch process to form a two level structure such as a via in a first metal layer connected to a metal line (in a trench) in a second metal layer.
The typical dual damascene process is to mask and etch a first layer of interlayer dielectric in the structure to form vias and then fill the vias with a conductive material. Once the vias have been formed, the next step is to form a second layer of interlayer dielectric on the first metal layer, mask and etch the second layer of interlayer dielectric to form trenches, and then fill the trenches with a conductive material. As is known in the semiconductor manufacturing art, the vias are in electrical contact with selected trenches to form a desired interconnect pattern, which forms an electrical circuit.
Each mask and etch step increases the total time and increases the complexity of the manufacturing process as well as potentially increasing the number of defects.
Therefore, what is needed is a manufacturing process for the forming of dual damascene structures that has a reduced number of mask and etch steps.